Method and system for short-circuit current modeling in CMOS integrated circuits

摘要: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy logic gate power dissipation models computer-based verification design tools. The model determines the short each complementary pair within a circuit. Input output voltage waveforms provided from results of timing analysis are used to behavior one device pair. is selected as limiting (the transitioning an “off state) direction transition being modeled, which also that not charging or discharging load. Therefore, through can be determined input equal prior saturation device. One more points generate polygonal waveform current, along with width (period) calculate directly.