CORDIC Processor with Carry-Save Architecture
作者： S. Wohlleben , T. Noll , H. Soldner , R. Kunemund
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摘要: A CORDIC processor for vector rotations using a carry-save architecture has been developed and realized. The algorithm is based on an iteration, directed by the sign of intermediate results. To achieve high clock frequency 60 MHz iteration was built up with pipelined adder stages. Due to redundant number representation exact detection not possible, so that had modified. throughput rate its regularity this well suited real-time applications.
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