作者: Dimitrios Ziakas , Allen Baum , Robert A. Maddox , Robert J. Safranek
DOI: 10.1109/HOTI.2010.24
关键词:
摘要: Single processor performance has exhibited substantial growth over the last three decades [1] as shown in Figure 1. What is also desired are techniques which enable connecting together multiple processors order to create scalable, modular and resilient multiprocessor systems. Beginning with production of Intel® Xeon® 5500 series, (previously codenamed “Nehalem-EP”), 7500 series “Nehalem-EX”), Itanium™ 9300 “Tukwila-MC”), Intel Corporation introduced a multi-core that can be easily interconnected server systems scaling from 2 8 sockets. In addition, OEM platforms currently available extend this up 256-socket designs1. This scalable system architecture built upon foundation QuickPath Interconnect (Intel QPI). These micro-architectures provide high-speed (currently 25.6 GB/s), point-to-point connections between processors, I/O hubs third party node controllers. The interconnect features, well capabilities into processor’s logic (also known “uncore”), work deliver performance, scalability, reliability demanded larger scale