Integrated circuit and method for low noise frequency synthesis

摘要: An integrated circuit device and method for synthesis of a signal having desired frequency low noise. The embodiment the invention generally includes phase locked loop (PLL) used in conjunction with multiplier. Specifically, multiplier connected to first input detector, pass filter between output detector voltage controlled oscillator (VCO), divider VCO second detector. produces that is multiple reference which For any frequency, use results smaller ratio "n" PLL, thereby reducing closed noise inside PLL bandwidth. Other embodiments include synthesis, clocking data onto SONET OC-48 channel. provides advantage