High throughput low-density parity-check decoder architectures

摘要: Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They applied to codes with matrices generated either randomly or using geometric properties of elements in Galois fields. Both have low computational requirements. The original concurrent schedule has a large storage requirement that is dependent on total number edges underlying bipartite graph, while new, staggered which uses an approximation belief propagation, reduced memory only bits block. performance these evaluated through simulations magnetic recording channel.