A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections

摘要: The ability to interconnect large numbers of integrated silicon devices on a single chip has been greatly aided by three-level wiring capability and solderable input/output terminals the face chip. This paper describes design process used fabricate interconnections IBM's most advanced bipolar devices. Among subjects discussed are thin film metallurgy contacts, e-beam lithography associated resist technology, high temperature lift-off stencil for metal pattern definition, planarized rf sputtered SiO 2 insulation/passivation, “zero-overlap” via hole innovation, in situ sputter cleaning vias prior metallization, area array solder terminals.