Automatic extraction of pipeline parallelism for embedded heterogeneous multi-core platforms

摘要: Automatic parallelization of sequential applications is the key for efficient use and optimization current future embedded multi-core systems. However, existing approaches often fail to achieve balancing tasks running on heterogeneous cores an MPSoC. A reason this insufficient knowledge underlying architecture's performance. In paper, we present a novel approach MPSoCs that combines pipeline loops with about different execution times performance properties. Using Integer Linear Programming, optimal solution respect model used derived implementing well-balanced behavior. We evaluate our using set standard benchmarks compare it two state-of-the-art approaches. For all benchmarks, obtains significantly higher speedups than either MPSoCs.