Process for the fabrication of dual gate structures for CMOS devices
作者： Joze Bevk
DOI:
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摘要: In accordance with the invention, a process for forming dual gate structure CMOS devices comprises steps of a) providing semiconductor workpiece including n-type and p-type regions dielectric region formed over regions, b) thin layer doped to one type conductivity, c) selectively removing overlying like conductivity doping d) opposite kind conductivity. The layers are then planarized as by chemical-mechanical polishing (CMP). An additional undoped can optionally be applied bury layers, device finished coating metal silicide in usual fashion. This completed only photolithography step, simplifying fabrication several operations.
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