System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code

摘要: A system and method for representing a level RTL hardware design using an HDL independent representation translation into synthesizable code. The present invention creates object-oriented library which can be used to implement designs in terms of objects. Instead implementing multiple instances modules, the enables software tool programmers one HDL-independent instance module. As result, programmer focus his efforts on generating functionality module relieved from time consuming task detailed syntax HDLs. also maintains synchronization across HDLs so that designer generate code any supported HDL, e.g., Verilog or VHDL, thus making maintenance easier.