Integrated circuit and method for issuing transactions
作者： Kees G. W. Goossens , Andrei Radulescu
DOI:
关键词:
摘要: An integrated circuit is provided comprising a plurality of processing modules (M, S) and network (N) arranged for coupling said S). Said comprises first module (M) encoding an atomic operation into transaction issuing to at least one second (S) . In addition, decoding means (TDM) the issued provided.
google.com.mx 参考文章(15)
Daniel L. Schweitzer, Donald B. Grosser, Michael D. Mroz, Rana Dayal, Methods and systems for hitless switch management module failover and upgrade ,(2003)
Teruyuki Maruyama, Multiprocessor system memory unit with split bus and method for controlling access to the memory unit ,(1997)
Atsushi Date, System controller using plural CPU's ,(2003)
D. Wiklund, Dake Liu, SoCBUS: switched network on chip for hard real time embedded systems international parallel and distributed processing symposium. pp. 78- ,(2003) , 10.1109/IPDPS.2003.1213180
G. Michael Uhler, Radhika Thekkath, Locked read/write on separate address/data bus using write barrier ,(1999)
A Andrei Radulescu, Kgw Kees Goossens, Communication services for networks on chip Domain-specific processors : systems, architectures, modeling and simulation. pp. 193- ,(2004)
Jon Ebbe Brelin, Method of and apparatus for cancelling a pending AV/C notify command ,(2001)
Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser, Active messages Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92. ,vol. 20, pp. 256- 266 ,(1992) , 10.1145/139669.140382
Neil C. Wilhelm, Hans Eberle, Method and apparatus for a pipelined network ,(2000)