Power efficiency for variation-tolerant multicore processors

摘要: Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of variability resulting timing instabilities leakage power variation. This work introduces an analytical approach ensuring reliability while the appropriate performance spite We validate our model using Turandot to simulate 8-core PowerPCtrade processor. first examine a simplified case on platform running independent multiprogrammed workloads consisting all 26 SPEC 2000 benchmarks. Our simple accurately predicts cutoff point with mean error less than 0.5 W. Next, we extend analysis parallel programming by incorporating Amdahl's law equations. use this relation establish limit properties power-performance scaling applications, findings 8 applications from SPLASH-2 benchmark suite