Run-Time Reconfiguration at Xilinx (invited talk)

摘要: Run-Time Reconfiguration (RTR) provides a powerful, but essentially untapped mode of operation for SRAM-based FPGAs. Research over the last decade has indicated that RTR can provide substantial benefits to system designers, both in terms overall performance and design simplicity. While holds great promise many aspects design, it only recently been considered commercial application. Two factors seem be converging make based viable. First, silicon process technology advanced point where million gate FPGA devices are commonplace. This permits larger, more complex algorithms directly implemented FGPAs. alone led quiet revolution design. Today, coprocessing using large coupled standard microprocessors is becoming commonplace, particularly Digital Signal Processing (DSP) applications. The second factor software. Until recently, there was literally no software support available RTR. Existing ASIC-based flows on schematic capture HDL did not necessary mechanisms allow implementation systems. JBits tool suite from Xilinx direct processing combination hardware already begun show some impressive results methodologies algorithms. Future plans enhance architectures tools such as should result widening acceptance this technology.