作者: Randeel Wimalagunarathne , Chamith Wijenayake , Arjuna Madanayake , Donald G. Dansereau , Len T. Bruton
DOI: 10.1007/S11045-013-0235-6
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摘要: Four-dimensional (4-D) infinite impulse response frequency hyper-planar filter and a digital VLSI architecture for real time light field based depth filtering applications is proposed. A signal flow graph on discrete spatial integrators introduced, which leads to improved sensitivity properties perturbations in coefficients. First order analysis of transfer function shows 92.9 % reduction maximum gain error with 12 bits fractional precision, when compared direct-form architecture. Prototype FPGA hardware-in-the-loop co-simulations are performed two different geometries. Register level design validation carried out via hardware emulation host computer providing memory buffers, the full-design standalone Berkely Emulation Engine (BEE3), operating at 36.44 37.31 MHz geometries, respectively. 45 nm CMOS implementation up synthesis level, yielding frequencies 154.4 153.3 (correspondingly frame rates 1.15 18.286 Hz)