A novel VLSI layout fabric for deep sub-micron applications

摘要: Proposes a new VLSI layout methodology which addresses the main problems faced in deep sub-micron (DSM) integrated circuit design. Our "fabric" scheme eliminates conventional notion of power and ground routing on die. Instead, are essentially "pre-routed" all over By clever arrangement power/ground signal pins, we almost completely eliminate capacitive effects between wires. Additionally. We get distribution network with very low resistance at any point Another advantage our is that conductors ensures on-chip inductances uniformly negligible. Finally, characterization delays, capacitances resistances becomes extremely simple scheme, needs to be done only once for show how uniform parasitics fabric give rise reliable predictable have implemented using public domain software. Preliminary results it holds much promise as choice DSM