High speed voltage level translator
作者： Hari Bilash Dubey , Anshu Vij
DOI:
关键词:
摘要: A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive low input signal control current translated signal. The further provides differential amplifier for receiving feedback signals thereby outputting
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