作者: Erkan Alpman , Hasnain Lakdawala , Marian Verhelst
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摘要: A wideband receiver back-end supporting dual band reception for carrier aggregation has been implemented in 32nm CMOS. The proposed architecture relies on tunable phase generation circuitries, feeding parallel paths consisting of a harmonic rejection mixer and ΔΣ-ADC. 3rd 5th order distortion is suppressed through statistical calibration, exploiting the inherent circuit variability, achieving HR3 HR5 jointly exceeding 70dB when tested across multiple dies, while dissipating 16mW per channel covering mixing range 240MHz.