Phase-locked loop signal generation system with control maintenance

摘要: A phase-locked loop system having as input a stable refernce clock signal and outputting master signal. The phase of the reference is compared to that pre-scaled difference represented by an analog error which converted digital A/D converter (116). then transformed into control D/A (120) applied VCO (128) generates signal, If has degraded or lost (116), receives its sampling in part from stops thus producing signals. last good maintained, maintained maintained.