Write leveling of memory units designed to receive access requests in a sequential chained topology

摘要: A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared when performing operations thereafter. Due such use signal, various desired delays can be determined accurately and/or easily. In embodiment, frequency is based on maximum fly-by delay (generally between sending shared sequential path and receipt at unit in sequence) that may system. For example, if fly by M (an integer) times time period normal operations, have operation.