Virtual address cache memory, processor and multiprocessor
作者： Kenta Yasufuku , Yasuhiko Kurosawa , Hiroo Hayashi , Mitsuo Saito , Shigeaki Iwasa
DOI:
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摘要: An embodiment provides a virtual address cache memory including: TLB page configured to, when rewrite to occurs, entry data; data hold using tag or offset as index; state for the stored in memory, association with first physical held address; and second is written after occurrence of TLB, address.
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