Ternary CAM cell with DRAM mask circuit

摘要: A ternary CAM cell including a binary SRAM connected in series with mask transistor between match line and discharge line, DRAM circuit for applying (care/don't care) value to the gate terminal of transistor. The stores data that is compared an applied value, opens first portion path when fails stored value. controlled by circuit, which includes two associated memory cells are bit sense amplifier. refreshed such that, during read phase refresh operation, only from registered (refreshed) amplifier circuit. In subsequent write written second cell. storage node