Bus interface logic system
作者： Thoi Nguyen , Mark Edward Dean
DOI:
关键词:
摘要: A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the control logic dividing concurrent address into an transaction followed transaction. During read operation, requesting device is forced to wait availability before entering write delayed using storage mechanism that effectively separates from The present invention also provides direct memory access fly-by operations input/output device. These are accomplished isolating secondary allowing destination capture requested as soon it available on bus.
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