A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS
作者： Jaspal Singh Shah , David Nairn , Manoj Sachdev
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摘要: A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T does not have dedicated access transistors, its quad-latch configuration stores data on four interlocked storage nodes. was designed in a 65-nm CMOS process. demonstrates excellent stability down to 0.55 V well suited for low-voltage, low-power applications. Neutron radiation testing the exhibits at least $ 15\times improvement Failure Time (FIT) rate compared conventional 6T technology.
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