Automatic protocol synthesizing system

摘要: An automatic protocol synthesizing system in which, incomplete state transition diagrams of at least two functionally processes forming a are received and completed the outputted. In accordance with present invention, there is provided checking circuit for making check logical error diagram an embedding embeds process corresponding to ith (where 1≦i≦N) one diagram. A generating automatically including all remaining (i+1)th subsequent processes, on basis embedded diagram; dividing divides thus synthesized into generated other processes. The operations circuit, repeated by (N-1) times complete each process, thereby complete.