Control circuit for an S-DRAM

摘要: Control circuit for a data path of an S-DRAM which is clocked by high-frequency clock signal, having programmable mode register storing latency value; generator temporally delaying control generated internal sequence controller, with switchable latency; decoder, switches the in manner dependent on value stored register, provision being made at least one signal delay element, can be switched decoder and serves specific time, switching associated element if high.