Apparatus for translation between virtual and physical addresses using page number, a physical page number, a process identifier and a global bit

作者: Masahide Kakeda , Reiji Segawa

DOI:

关键词:

摘要: An address translation apparatus comprises: entry storage means for storing a plurality of entries, each containing virtual page number, physical and process identifier which is composed plural bits; comparison information defines method comparing possessed by that currently executed, with the in entry; comprising entry, on basis information; retrieval retrieving, from means, an including number equal to supplied outside, matches executed process, according result means. Therefore, when memory has content can be shared between at least two processes, effective utilization area achieved unifying entries respect these processes.

参考文章(11)
Richard J. Burgess, Jay B. Miller, Mark A. Schaecher, Low power cache operation through the use of partial tag comparison ,(1999)
Randall G. Banton, Douglas E. Jewett, Richard W. Cutts, Fault-tolerant computer system having switchable I/O bus interface modules ,(1995)
Allen W. Roberts, Timothy P. Layman, P. Michael Farmwald, Huy Xuan Ngo, George S. Taylor, Software invalidation in a multiple level, multiple cache system ,(1995)
David J. Sager, Glenn J. Hinton, Way-predicting cache memory ,(1999)
Ravi Kumar Arimilli, Guy Lynn Guthrie, Jerry Don Lewis, Jody B. Joyner, John Steven Dodson, Cache index based system address bus ,(1999)