Data sampling and recover in a phase-locked loop (PLL)

摘要: A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent signals, phase-locked loop (PLL) is aligned with incoming data, comprising: data sampler sampling bits the each wherein first signals clocks 0, 0+n, 0+2n, . , and second 1, 1+n, 1+2n, Also, PLL recovering signal from generator generating an odd number, n, signals; data; pair outputs sampler, use in phase detector (along data), capable producing adjustment output. Another characterization method comprising steps of: to PLL; Similarly, third can be used 2, 2+n, 2+2n, as well fourth fifth signals.