摘要: This paper addresses a fast low-power implementation of shared division and square-root architecture. Two approaches are considered in this paper; these include the SRT (Sweeney, Robertson Tocher) approach which does not require prescaling GST (generalized Svoboda Tung) requires operands. makes two important contributions. Although have been known for long time, architectures based on proposed so far. first develops architecture without requiring an additional by scaling factor after operation. various divider compared with respect to speed, no tradeoffs power consumption studied far quantitative comparison speed division/square-root units is second main contribution paper. Shared designed approaches, both minimally maximally redundant radix-4 representations. Simulations demonstrate that worst-case overall latency minimally-redundant 35% smaller SRT. Alternatively, fixed latency, operations consume 42% 20% less respectively, maximally-redundant approach.
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