System and method for debugging system-on-chips using single or n-cycle stepping

摘要: Large, complex SoCs comprise interconnections of various functional blocks, which blocks frequently running on different clock domains. By effectively controlling the clocks within SoC, this invention provides a means to halt execution SoC and then single or n-cycle step its in real system environment. Accordingly, an effective debugging tool both designer software designers whose code is executed by as it them capability studying cause effect interactions between blocks. The also applicable containing only one block while circuitry operating than block's clock. In particular, permits halting stepping permit analysis circuitry.