Synthesis Techniques for Built-In Self-Testable Designs

作者: LaNae J Avra

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摘要: This technical report contains the text of LaNae Joy Avra''s thesis "Synthesis Techniques for Built-In Self-Testable Designs."

参考文章(56)
B. Koenemann, Built-in logic block observation techniques Proc. 1979 IEEE Test Conf.. pp. 37- 41 ,(1979)
LaNae J. Avra, Edward J. McCluskey, Laurent Gerbaux, Jean Giomi, Francoise Martinolle, A Synthesis-for-Test Design System Stanford University. ,(1994)
Andrzej Krasniewski, Alexander Albicki, Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. international test conference. pp. 362- 371 ,(1985)
William H. McAnney, Paul H. Bardell, Self-Testing of Multichip Logic Modules. international test conference. pp. 200- 204 ,(1982)
L. Avra, Orthogonal built-in self-test Digest of Papers COMPCON Spring 1992. pp. 452- 457 ,(1992) , 10.1109/CMPCON.1992.186754
R. Patel, K. Yarlagadda, Testability features of the SuperSPARC microprocessor international test conference. pp. 773- 781 ,(1993) , 10.1109/TEST.1993.470625
William H. McAnney, Paul H. Bardell, Jacob Savir, Built In Test for VLSI: Pseudorandom Techniques ,(1987)
K. Yokomizo, K. Naito, A 333 MHz, 72 Kb BiCMOS pipelined buffer memory with built-in self test symposium on vlsi circuits. pp. 32- 33 ,(1992) , 10.1109/VLSIC.1992.229250
P.H. Bardell, M.J. Lapointe, Production experience with built-in self-test in the IBM ES/9000 system international test conference. pp. 28- 36 ,(1991) , 10.1109/TEST.1991.519490
R. Illman, T. Bird, G. Catlow, S. Clarke, L. Theobald, G. Willetts, Built-in self-test of the VLSI content addressable filestore international test conference. pp. 37- 46 ,(1991) , 10.1109/TEST.1991.519492