Low voltage CMOS circuit for on/off chip drive at high voltage

摘要: A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high off-chip drivers while protecting the devices from various breakdown mechanisms. The utilize intermediate voltages between two power rails division techniques to limit acceptable limits for drain-to-source, gate-to-drain, gate-to-source in any chosen technology. comprises first second cascode chains connected a rail, e.g 5 volt reference potential e.g. ground. Each chain p-type MOS series with n-type devices. An input is coupled node at midpoint chain. bias voltage, typically 3.3 volts NMOS chains. PMOS provided third purposes providing sufficient pullup capability drive an comprising fourth potentials without exceeding mechanisms device