Digital processing apparatus using two synchronization signals
作者： Hidemi Oka , Kiyokazu Hashimoto , Iwao Hidaka , Takao Kashiro , Yoshiki Yamamoto
DOI:
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摘要: The digital processing apparatus includes a high speed response PLL that produces first clock signal locked on the horizontal synchronization included in video input thereto. An analog to converter converts with respect into digitized signal. A write controller controls memory store based low second vertical read out stored therefrom control can and from stably, enabling be processed effectively securely.
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