Virtual wires: overcoming pin limitations in FPGA-based logic emulators

摘要: Existing FPGA-based logic emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to single emulated signal (logical wire). Virtual wires overcome limitations by intelligently multiplexing physical wire among multiple logical and pipelining these connections at the maximum clocking frequency FPGA. A virtual represents connection from output on one input another not increase usable bandwidth, but also relax absolute limits imposed gate utilization. The resulting improvement in reduces need for global interconnect, allowing effective low dimension inter-chip (such as nearest-neighbor). Nearest-neighbor topologies, coupled with ability overlap computation, can even improve emulation speeds. authors present concept describe their first implementation, 'softwire' compiler which utilizes static routing relies minimal hardware support. Results compiling netlists 18 K Sparcle microprocessor 86 Alewife Communications Cache Controller indicate that utilization beyond 80 percent without significant slowdown speed. >