Blocking Linear Algebra Codes for Memory Hierarchies

摘要: Because computation speed and memory size are both increasing, the latency of memory, in basic machine cycles, is also increasing. As a result, recent compiler research has focused on reducing e ective by restructuring programs to take more advantage high-speed intermediate (or cache, as it usually called). The problem that many real-world non-trivial restructure, current methods will often fail. In this paper, we present some encouraging preliminary results project determine how much possible with automatic techniques.