Non-volatile electrically erasable memory with PMOS transistor NAND gate structure

摘要: A NAND Flash EEPROM string is formed in a common N-well and includes plurality of P-channel MOS stacked-gate storage transistors ground select transistors. In the preferred embodiment, each transistor programmed via hot electron injection from depletion region proximate its P+ drain/N-well junction erased tunneling floating gate to P-type channel as well source drain regions without requiring high programming erasing voltages, respectively. Further, P/N biases are not required during or operations. This allows dimensions present embodiments be reduced size smaller than that comparable conventional N-channel strings.