Circuit test system electric element memory control chip under different test modes

作者: Wen-Chang Cheng

DOI:

关键词:

摘要: A circuit test system including a apparatus and to be tested is provided. The provides first clock signal. includes plurality of input/output pads at least one pad. At two the are connected each other form loop during mode. pad receives multiplies frequency signal generate second signal, based on higher than that Furthermore, method foregoing also

参考文章(18)
Dan Lunecki, Terry L. Lyon, Dennis L. Wendell, Charles Hochstedler, Clock signal multiplier ,(1990)
Kwansuhk Oh, Himanshu J. Verma, Signal adjustment for duty cycle control ,(2005)
Herve Philips Ip Standards Fleury, Jean-marc Philips Ip Standards Yannou, Testable electronic circuit ,(2006)
Yumiko Hashidume, Takashi Hattori, Tatsuhiro Nishino, Kouji Ikeda, Semiconductor apparatus and test method therefor ,(2007)