Optimizing multi-level combinational circuits for generating random bits

摘要: Random bits are an important construct in many applications, such as hardware-based implementation of probabilistic algorithms and weighted random testing. One approach generating with required probabilities is to synthesize combinational circuits that transform a set source into target probabilities. In [1], the authors proposed greedy algorithm synthesizes form gate chain approximate However, since this only considers special form, resulting not satisfactory both terms approximation error circuit depth. paper, we propose new for bits. Compared previous one, our greatly enlarges search space. Also, apply linear property logic computation iterative local method increase efficiency algorithm. Experimental results comparing errors depths synthesized by those demonstrate superiority method.