Synchronous timing scheme for a data processing system

摘要: A scheme for synchronizing the transfer of information signals between a Line Terminal and an associated Modem at computer site data processing system. The involves addition logical circuit, termed Synchronous Timing Assembly, to already existing Terminal. added Assembly resynchronizes generated receive clock signal each time two incoming signals, such as Mark Space that are received sequentially from Modem, differ in state. Additionally, enables discriminate valid invalid by dropping out all not meeting established criteria.