作者: Veerendra Bhora , Tibor Boros , Pulakesh Roy
DOI:
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摘要: The present invention allows a complex digital processing engine (18) to be tested automatically and autonomously using minimum of memory resources. In one embodiment, the includes test controller (48) integrated on an IC (14), pattern generator (46) coupled provide upon receiving command, unit under receive start signal from apply operation pattern, generating output. It further buffer (30) store representation output, reference (44) value, comparator (42) compare contents stored value result controller.