Programmable address translation system
作者： Roger L. Gilbertson , Mitchell A. Bauman
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摘要: A programmable address translation system for a modular main memory is provided. The implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical predetermined range within the system. Predetermined bits of logical are used to associated with range. Data read from then substituted form physical address. In this manner, non-contiguous addressable banks may be mapped selectable contiguous By including Address number N addresses, an mechanism provided which programmed perform between 2-way and 2 -way interleaving. Each re-programmed dynamically accommodate changing conditions as occur, example, when logically removed because errors. Furthermore, reprogramming occur while operations continue other non-associated ranges. Additionally, interleaving selected certain ones ranges, whereas non-interleaving scheme
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