Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system

摘要: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on ring has host processor with CPU, main memory, and system bus. The device, operating relatively independent is coupled to memory by bus includes read/write on-chip timer, arbiter. transmit/receive controller connected between device. This directly access also under control CPU executes instructions fetched from ROM accessed bus, so instruction fetch, direct transmitting or receiving data frames, copying transmitted received message all contend Bus arbitration appropriate priorities timer provides time period monitor protocol.