Silicon on insulator and thin film transistor bandgap engineered split gate memory
作者： Hang-Ting Lue , Erh-Kun Lai
DOI:
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摘要: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The comprise channel region semiconductor strip formed on an insulating layer; tunnel dielectric structure disposed above the region, multilayer including at least one layer having hole-tunneling barrier height lower than that interface with region; charge storage structure; and gate electrode Arrays methods of operation are described.
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