Combination multiplexer and tristate driver circuit

作者: Daniel W. Dobberphul

DOI:

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摘要: A combination multiplexer and tristate circuit. circuit may be configured to receive at least a first data input second input, which are selected by select signal signal, respectively. is provide an output node responsive the that corresponding being active. The further use circuit, also coupled signal. If neither nor active, then prevent from providing node.

参考文章(14)
Clarence R. Ogilvie, Stephen B. Barrett, Tree-type multiplexers and methods for configuring the same ,(1991)
Tuan P. Do, Brian J. Campbell, Circuit for lines with multiple drivers ,(2003)
Ralph D. Wittig, Sundararajarao Mohan, Method for implementing large multiplexers with FPGA lookup tables ,(2000)
Tuan P Do, Brian J Campbell, High-speed bank select multiplexer latch ,(2001)
Ralph D. Wittig, Sundararajarao Mohan, Bernard J. New, FPGA logic element with variable-length shift register capability ,(2002)
Roman Iwanczuk, Trevor J. Bauer, Kamal Chaudhary, Shekhar Bapat, Steven P. Young, Configurable logic element with ability to evaluate five and six input functions ,(1997)
Eric Bernard Schorn, Marlin Wayne Frederick, Donald George Mikan, High performance dynamic multiplexers without clocked NFET ,(1998)