Fault Detection and Design For Testability of CMOS Logic Circuits
作者： Sudhakar M. Reddy , Sandip Kundu
DOI: 10.1007/978-94-009-1417-9_4
关键词:
摘要: Advances in integrated circuit technologies have made complementary MOS (CMOS) the preferred technology for digital logic circuits. Cost effective design and fabrication of reliable CMOS VLSI chips require understanding various technologies, families, failure modes, fault detection methods testability methods. In this paper we will review some basic issues related to
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