Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system

摘要: A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in multi-processor computer system is provided which capable (1) detecting when one set predefined inconsistency states occurs as transaction request being processed, (2) correcting so that operation may be executed correct consistent manner. In particular, adapted to address two kinds states: from unit location written present some unit-in such case, "stale" avoided by preventing associated using data; read requested or has already been processor--in this returned requesting updated cache. The presence above-described detected SCU-based multi-processing providing SCU with means maintaining copy directories each caches. continually compares accompanying access requests what stored order determine conditions indicative inconsistencies, subsequently executes corresponding fix-up sequences.