Memory system and method to reduce reflection and signal degradation

摘要: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment is divided on motherboard component routed to each two dual in-line modules (DIMMs) two-DIMM/channel design. The DIMM then sequentially through dynamic random access (DRAM) chip respective DIMM. In embodiment, after routing DRAM, terminated an alternative die at last DRAM