A systolic architecture based GF (2m) multiplier using modified LSD first multiplication algorithm
作者： Aaditi Bhoite , P.V.S. Shastry , Manasi Rashinkar
DOI: 10.1109/TENCON.2015.7373168
关键词:
摘要: This paper presents GF(2m) multiplier for trinomials. Multiplier is implemented using digit serial/parallel architecture. Architecture constructed modified LSD-first multiplication algorithm. Bit throughput a critical factor of different applications.Applications such as digital signal processors, computer systems, FIR filter implementation. architecture achieves latency m/d clock cycles along with high bit m-bits per cycles. Whereas, m no. input bits each operand. And d selected size. always greater than d.
sci-hub.se 参考文章(10)
Somsubhra Talapatra, Hafizur Rahaman, Samir K. Saha, Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m) digital systems design. pp. 427- 432 ,(2010) , 10.1109/DSD.2010.59
Jiafeng Xie, Pramod Kumar Meher, Jianjun He, Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing 2012 IEEE International Symposium on Circuits and Systems. pp. 89- 92 ,(2012) , 10.1109/ISCAS.2012.6272184
George N. Selimis, Apostolos P. Fournaris, Harris E. Michail, Odysseas Koufopavlou, Improved throughput bit-serial multiplier for GF(2m) fields Integration. ,vol. 42, pp. 217- 226 ,(2009) , 10.1016/J.VLSI.2008.07.003
Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher, Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields IEEE Transactions on Circuits and Systems. ,vol. 60, pp. 3195- 3204 ,(2013) , 10.1109/TCSI.2013.2264694
Jiafeng Xie, Pramod Kumar Meher, Jianjun He, Low-Complexity Multiplier for $GF(2^{m})$ Based on All-One Polynomials IEEE Transactions on Very Large Scale Integration Systems. ,vol. 21, pp. 168- 173 ,(2013) , 10.1109/TVLSI.2011.2181434
Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon, A digit-serial multiplier for finite field GF(2/sup m/) IEEE Transactions on Very Large Scale Integration Systems. ,vol. 13, pp. 476- 483 ,(2005) , 10.1109/TVLSI.2004.842923
S. Kumar, T. Wollinger, C. Paar, Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography IEEE Transactions on Computers. ,vol. 55, pp. 1306- 1311 ,(2006) , 10.1109/TC.2006.165
J.L. Imana, J.M. Sanchez, F. Tirado, Bit-parallel finite field multipliers for irreducible trinomials IEEE Transactions on Computers. ,vol. 55, pp. 520- 533 ,(2006) , 10.1109/TC.2006.69
P.K. Meher, Systolic and Super-Systolic Multipliers for Finite Field $GF(2^{m})$ Based on Irreducible Trinomials IEEE Transactions on Circuits and Systems. ,vol. 55, pp. 1031- 1040 ,(2008) , 10.1109/TCSI.2008.916622
P.K. Meher, Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed–Solomon Codec IEEE Transactions on Very Large Scale Integration Systems. ,vol. 17, pp. 747- 757 ,(2009) , 10.1109/TVLSI.2008.2006080