Basic Design of a Josephson Technology Cache Memory

摘要: Design work on components for Josephson computer technology nondestructive read out cache memories has been published previously. In this paper, presenting a design 2.5-µm technology, 4 × 1K-bit chip with nominal access time of about 500 ps as basis, we show the first how these are structured and interfaced. The cell, drivers, decoder, sense bus based designs which were experimentally verified in 5-µm excellent agreement was found between simulations measurements.