Power gating circuit

作者: Tetsuya Fujita

DOI:

关键词:

摘要: A semiconductor integrated circuit includes a first power supply line to which an input voltage is be applied, second configured bias load circuit, MOS transistor having source-drain current path connected between the and lines, NMOS control generate signal that supplied gate electrode of PMOS at point in time, boosted have level higher than then time after time.

参考文章(13)
Sureshkumar Govindaraj, Jose L. Flores, Reconfigurable power switch chains for efficient dynamic power saving ,(2014)
Jang-Hwan Yoon, Jin-Sung Kim, Sang-Yeop Baeck, Power gating circuit ,(2013)
John P Biggs, David W Howard, David W Flynn, James E Myers, Integrated circuit and method for generating a layout of such an integrated circuit ,(2012)
David William Howard, David Walter Flynn, Sachin Satish Idgunji, Robert Campbell Aitken, Integrated circuit power-on control and programmable comparator ,(2007)
Bharath Upputuri, Bruce Kauffmann, Ray Bloker, Method and circuit for reducing current surge ,(2012)
Igarashi Masahiro, Kaneko Ryuji, Ogata Hiromi, Motomura Tetsuo, Fujiwara Makoto, Tanaka Yoshinori, SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS POWER SUPPLY CONTROL METHOD ,(2009)