Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration

摘要: A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to processor, includes: beginning an execution of application by processor; receiving instruction from processor perform function application; determining that FPGA is not programmed with logic function; fetching configuration bit stream and stream. In this manner, are programmable “on fly”, i.e., during application. The hardware acceleration resource sharing advantages provided can be utilized more often Logic flexibility space savings on chip comprising as well.