Data handling system for handling data transfers between a cache memory and a main memory
作者： Jerrold L. Allen
DOI:
关键词:
摘要: In a data handling system having one or more processors, cache memory associated with each processor and main unit, is divided into an equal number of portions, the corresponding portions. A transfer bus provided between group portions portion such that corresponds to only memory. Each in independently controlled rate transfers for as whole increased.
lens.org 参考文章(8)
Graham C Driscoll, Edward H Sussenguth, Input-output control system for data processing apparatus ,(1967)
Bruce H. Tarbox, John J. Bradley, Ralph M. Lombardo, John W. Conway, Kenneth E. Bruce, Intersystem cycle control logic ,(1981)
David B. Schuck, James E. Kocol, Daniel J. Marro, Robert O. Gunderson, Data processing system wherein at least one subsystem has a local memory and a mailbox memory within the local memory for storing header information ,(1981)
Philip E. Stanley, Arthur Peters, Data steering logic for the output of a cache memory having an odd/even bank structure ,(1980)
Edwin P. Fisher, James W. Keeley, John L. Curley, Multilevel cache system with graceful degradation capability ,(1982)
Philip E. Stanley, Richard P. Brown, Arthur Peters, Odd/even bank structure for a cache memory ,(1980)
Barner R, Alvarez J, Memory system with logical and real addressing ,(1972)
Albert H. Schwartz, Automatic memory module address assignment system for available memory modules ,(1981)